This invention relates to phase decoders and more particularly, to a digital phase decoder for a data communication system of the type comprising a communicating medium, a plurality of transceivers connected to the medium, and means for interrupting the transmission of data onto the medium by one transceiver when that same transceiver receives data transmitted by another transceiver.
An example of a data communications system of the above-type is disclosed in U.S. Pat. No. 4,063,220. As described in that patent, a collision detector is provided with each transceiver for detecting when the data on the medium differs from the data being communicated by the associated transceiver. A detected difference indicates a "collision" between the signal being transmitted by the associated transceiver and a signal from another transceiver. In response to the detected collision, a collision signal is generated. This signal is then sensed by appropriate means to interrupt transmission by the associated transceiver.
As also described in U.S. Pat. No. 4,063,220, data received by a transceiver connected to the communicating medium is forwarded to a phase decoder which basically separates the data and clock components of the received data. Both data and clock component signals are then respectively applied to the data and clock inputs of a shift register. The shift register converts the serial input data stream into parallel data words of predetermined bit-length, e.g., 16-bit words, for transmittal through a synchronizing buffer register onto a data bus for transfer to a using device.
One problem with phase decoders of the type disclosed in U.S. Pat. No. 4,063,220, is that they use analog circuitry, at least in part, to separate the clock and data components of the phase encoded input. As is well known, analog circuitry tends to drift out of adjustment, which may cause decoding inaccuracies. Further, a completely digital phase decoder is more amemable to microelectronics integration.